#ifndef __SPI_REG_H__
#define __SPI_REG_H__

#ifndef __KERNEL__
#ifdef __cplusplus
extern "c" {
#endif
#endif


#define __REG_SPI_BASE		( REG_SPI_BASE )


#define R_SPI_CTRL0		( __REG_SPI_BASE + 0x0 )

/**
 bitpos: [3:0]
 data frame size
 */
#define F_SPI_0000_DFS 0x0000000F
#define F_SPI_0000_DFS_M 0x0000000F
#define F_SPI_0000_DFS_V 0xF
#define F_SPI_0000_DFS_S 0
/**
 bitpos: [5:4]
 00:Motorola SPI
 01:TI SSP
 10:National semiconductors MicroWire
 11:reserved
 */
#define F_SPI_0000_FRF 0x00000030
#define F_SPI_0000_FRF_M 0x00000030
#define F_SPI_0000_FRF_V 0x3
#define F_SPI_0000_FRF_S 4
/**
 bitpos: [6]
 0: Inactive state of serial clock is low
 1: Inactive state of serial clock is high
 */
#define F_SPI_0000_SCPH 0x00000040
#define F_SPI_0000_SCPH_M 0x00000040
#define F_SPI_0000_SCPH_V 0x1
#define F_SPI_0000_SCPH_S 6
/**
 bitpos: [7]
 0: Inactive state of serial clock is low
 1: Inactive state of serial clock is high
 */
#define F_SPI_0000_SCPOL 0x00000080
#define F_SPI_0000_SCPOL_M 0x00000080
#define F_SPI_0000_SCPOL_V 0x1
#define F_SPI_0000_SCPOL_S 7
/**
 bitpos: [9:8]
 00: TX & RX
 01: TX only
 10: RX only
 11: eeprom read
 */
#define F_SPI_0000_TMOD 0x00000300
#define F_SPI_0000_TMOD_M 0x00000300
#define F_SPI_0000_TMOD_V 0x3
#define F_SPI_0000_TMOD_S 8
/**
 bitpos: [10]
 0: no toggle
 1: toggle cs between data frames
 */
#define F_SPI_0000_CS_TGL 0x00000400
#define F_SPI_0000_CS_TGL_M 0x00000400
#define F_SPI_0000_CS_TGL_V 0x1
#define F_SPI_0000_CS_TGL_S 10
/**
 bitpos: [11]
 0: normal mode
 1: test mode
 */
#define F_SPI_0000_SRL_TEST 0x00000800
#define F_SPI_0000_SRL_TEST_M 0x00000800
#define F_SPI_0000_SRL_TEST_V 0x1
#define F_SPI_0000_SRL_TEST_S 11
/**
 bitpos: [15:12]
 control frame size for MicroWire frame format
 */
#define F_SPI_0000_CFS 0x0000F000
#define F_SPI_0000_CFS_M 0x0000F000
#define F_SPI_0000_CFS_V 0xF
#define F_SPI_0000_CFS_S 12

#define R_SPI_CTRL1		( __REG_SPI_BASE + 0x4 )

/**
 bitpos: [15:0]
 number of data frames, actually plus 1
 */
#define F_SPI_0004_NDF 0x0000FFFF
#define F_SPI_0004_NDF_M 0x0000FFFF
#define F_SPI_0004_NDF_V 0xFFFF
#define F_SPI_0004_NDF_S 0

#define R_SPI_SSIENR		( __REG_SPI_BASE + 0x8 )

/**
 bitpos: [0]
 */
#define F_SPI_0008_SSI_EN 0x00000001
#define F_SPI_0008_SSI_EN_M 0x00000001
#define F_SPI_0008_SSI_EN_V 0x1
#define F_SPI_0008_SSI_EN_S 0

#define R_SPI_MVCR		( __REG_SPI_BASE + 0xC )

/**
 bitpos: [0]
 Microwire handshaking
 */
#define F_SPI_000C_MWMOD 0x00000001
#define F_SPI_000C_MWMOD_M 0x00000001
#define F_SPI_000C_MWMOD_V 0x1
#define F_SPI_000C_MWMOD_S 0
/**
 bitpos: [1]
 Microwire control
 */
#define F_SPI_000C_MDD 0x00000002
#define F_SPI_000C_MDD_M 0x00000002
#define F_SPI_000C_MDD_V 0x1
#define F_SPI_000C_MDD_S 1
/**
 bitpos: [2]
 Microwire transfer mode
 */
#define F_SPI_000C_MHS 0x00000004
#define F_SPI_000C_MHS_M 0x00000004
#define F_SPI_000C_MHS_V 0x1
#define F_SPI_000C_MHS_S 2

#define R_SPI_SER		( __REG_SPI_BASE + 0x10 )

/**
 bitpos: [0]
 */
#define F_SPI_0010_SER 0x00000001
#define F_SPI_0010_SER_M 0x00000001
#define F_SPI_0010_SER_V 0x1
#define F_SPI_0010_SER_S 0

#define R_SPI_BAUDR		( __REG_SPI_BASE + 0x14 )

/**
 bitpos: [15:0]
 ssi clock divder
 */
#define F_SPI_0014_SCKDV 0x0000FFFF
#define F_SPI_0014_SCKDV_M 0x0000FFFF
#define F_SPI_0014_SCKDV_V 0xFFFF
#define F_SPI_0014_SCKDV_S 0

#define R_SPI_TXFTLR		( __REG_SPI_BASE + 0x18 )

/**
 bitpos: [3:0]
 tx fifo threshold, <= value will assert ssi_txe_intr(txeir)
 */
#define F_SPI_0018_TFT 0x0000000F
#define F_SPI_0018_TFT_M 0x0000000F
#define F_SPI_0018_TFT_V 0xF
#define F_SPI_0018_TFT_S 0

#define R_SPI_RXFTLR		( __REG_SPI_BASE + 0x1C )

/**
 bitpos: [3:0]
 rx fifo threshold, >= (value+1) will assert ssi_rxf_intr(rxfir)
 */
#define F_SPI_001C_RFT 0x0000000F
#define F_SPI_001C_RFT_M 0x0000000F
#define F_SPI_001C_RFT_V 0xF
#define F_SPI_001C_RFT_S 0

#define R_SPI_TXFLR		( __REG_SPI_BASE + 0x20 )

/**
 bitpos: [4:0]
 tx fifo level
 */
#define F_SPI_0020_TXTFL 0x0000001F
#define F_SPI_0020_TXTFL_M 0x0000001F
#define F_SPI_0020_TXTFL_V 0x1F
#define F_SPI_0020_TXTFL_S 0

#define R_SPI_RXFLR		( __REG_SPI_BASE + 0x24 )

/**
 bitpos: [4:0]
 rx fifo level
 */
#define F_SPI_0024_RXTFL 0x0000001F
#define F_SPI_0024_RXTFL_M 0x0000001F
#define F_SPI_0024_RXTFL_V 0x1F
#define F_SPI_0024_RXTFL_S 0

#define R_SPI_SR		( __REG_SPI_BASE + 0x28 )

/**
 bitpos: [0]
 ssi busy flag
 */
#define F_SPI_0028_BUSY 0x00000001
#define F_SPI_0028_BUSY_M 0x00000001
#define F_SPI_0028_BUSY_V 0x1
#define F_SPI_0028_BUSY_S 0
/**
 bitpos: [1]
 tx fifo not full
 */
#define F_SPI_0028_TFNF 0x00000002
#define F_SPI_0028_TFNF_M 0x00000002
#define F_SPI_0028_TFNF_V 0x1
#define F_SPI_0028_TFNF_S 1
/**
 bitpos: [2]
 tx fifo empty
 */
#define F_SPI_0028_TFE 0x00000004
#define F_SPI_0028_TFE_M 0x00000004
#define F_SPI_0028_TFE_V 0x1
#define F_SPI_0028_TFE_S 2
/**
 bitpos: [3]
 rx fifo not empty
 */
#define F_SPI_0028_RFNE 0x00000008
#define F_SPI_0028_RFNE_M 0x00000008
#define F_SPI_0028_RFNE_V 0x1
#define F_SPI_0028_RFNE_S 3
/**
 bitpos: [4]
 rx fifo full
 */
#define F_SPI_0028_RFF 0x00000010
#define F_SPI_0028_RFF_M 0x00000010
#define F_SPI_0028_RFF_V 0x1
#define F_SPI_0028_RFF_S 4
/**
 bitpos: [6]
 tx data collision error
 */
#define F_SPI_0028_DCOL 0x00000040
#define F_SPI_0028_DCOL_M 0x00000040
#define F_SPI_0028_DCOL_V 0x1
#define F_SPI_0028_DCOL_S 6

#define R_SPI_IMR		( __REG_SPI_BASE + 0x2C )

/**
 bitpos: [0]
 tx fifo empty interrupt mask
 */
#define F_SPI_002C_TXEIM 0x00000001
#define F_SPI_002C_TXEIM_M 0x00000001
#define F_SPI_002C_TXEIM_V 0x1
#define F_SPI_002C_TXEIM_S 0
/**
 bitpos: [1]
 tx fifo overflow interrupt mask
 */
#define F_SPI_002C_TXOIM 0x00000002
#define F_SPI_002C_TXOIM_M 0x00000002
#define F_SPI_002C_TXOIM_V 0x1
#define F_SPI_002C_TXOIM_S 1
/**
 bitpos: [2]
 rx fifo underflow interrupt mask
 */
#define F_SPI_002C_RXUIM 0x00000004
#define F_SPI_002C_RXUIM_M 0x00000004
#define F_SPI_002C_RXUIM_V 0x1
#define F_SPI_002C_RXUIM_S 2
/**
 bitpos: [3]
 rx fifo overflow interrupt mask
 */
#define F_SPI_002C_RXOIM 0x00000008
#define F_SPI_002C_RXOIM_M 0x00000008
#define F_SPI_002C_RXOIM_V 0x1
#define F_SPI_002C_RXOIM_S 3
/**
 bitpos: [4]
 rx fifo full interrupt mask
 */
#define F_SPI_002C_RXFIM 0x00000010
#define F_SPI_002C_RXFIM_M 0x00000010
#define F_SPI_002C_RXFIM_V 0x1
#define F_SPI_002C_RXFIM_S 4
/**
 bitpos: [5]
 spi master done interrupt mask
 */
#define F_SPI_002C_MSTIM 0x00000020
#define F_SPI_002C_MSTIM_M 0x00000020
#define F_SPI_002C_MSTIM_V 0x1
#define F_SPI_002C_MSTIM_S 5

#define R_SPI_ISR		( __REG_SPI_BASE + 0x30 )

/**
 bitpos: [0]
 tx fifo empty interrupt status
 */
#define F_SPI_0030_TXEIS 0x00000001
#define F_SPI_0030_TXEIS_M 0x00000001
#define F_SPI_0030_TXEIS_V 0x1
#define F_SPI_0030_TXEIS_S 0
/**
 bitpos: [1]
 tx fifo overflow interrupt status
 */
#define F_SPI_0030_TXOIS 0x00000002
#define F_SPI_0030_TXOIS_M 0x00000002
#define F_SPI_0030_TXOIS_V 0x1
#define F_SPI_0030_TXOIS_S 1
/**
 bitpos: [2]
 rx fifo underflow interrupt status
 */
#define F_SPI_0030_RXUIS 0x00000004
#define F_SPI_0030_RXUIS_M 0x00000004
#define F_SPI_0030_RXUIS_V 0x1
#define F_SPI_0030_RXUIS_S 2
/**
 bitpos: [3]
 rx fifo overflow interrupt status
 */
#define F_SPI_0030_RXOIS 0x00000008
#define F_SPI_0030_RXOIS_M 0x00000008
#define F_SPI_0030_RXOIS_V 0x1
#define F_SPI_0030_RXOIS_S 3
/**
 bitpos: [4]
 rx fifo full interrupt status
 */
#define F_SPI_0030_RXFIS 0x00000010
#define F_SPI_0030_RXFIS_M 0x00000010
#define F_SPI_0030_RXFIS_V 0x1
#define F_SPI_0030_RXFIS_S 4
/**
 bitpos: [5]
 spi master done interrupt status
 */
#define F_SPI_0030_MSTIS 0x00000020
#define F_SPI_0030_MSTIS_M 0x00000020
#define F_SPI_0030_MSTIS_V 0x1
#define F_SPI_0030_MSTIS_S 5

#define R_SPI_RISR		( __REG_SPI_BASE + 0x34 )

/**
 bitpos: [0]
 tx fifo empty raw interrupt status
 */
#define F_SPI_0034_TXEIR 0x00000001
#define F_SPI_0034_TXEIR_M 0x00000001
#define F_SPI_0034_TXEIR_V 0x1
#define F_SPI_0034_TXEIR_S 0
/**
 bitpos: [1]
 tx fifo overflow raw interrupt status
 */
#define F_SPI_0034_TXOIR 0x00000002
#define F_SPI_0034_TXOIR_M 0x00000002
#define F_SPI_0034_TXOIR_V 0x1
#define F_SPI_0034_TXOIR_S 1
/**
 bitpos: [2]
 rx fifo underflow raw interrupt status
 */
#define F_SPI_0034_RXUIR 0x00000004
#define F_SPI_0034_RXUIR_M 0x00000004
#define F_SPI_0034_RXUIR_V 0x1
#define F_SPI_0034_RXUIR_S 2
/**
 bitpos: [3]
 rx fifo overflow raw interrupt status
 */
#define F_SPI_0034_RXOIR 0x00000008
#define F_SPI_0034_RXOIR_M 0x00000008
#define F_SPI_0034_RXOIR_V 0x1
#define F_SPI_0034_RXOIR_S 3
/**
 bitpos: [4]
 rx fifo full raw interrupt status
 */
#define F_SPI_0034_RXFIR 0x00000010
#define F_SPI_0034_RXFIR_M 0x00000010
#define F_SPI_0034_RXFIR_V 0x1
#define F_SPI_0034_RXFIR_S 4
/**
 bitpos: [5]
 spi master done raw interrupt status
 */
#define F_SPI_0034_MSTIR 0x00000020
#define F_SPI_0034_MSTIR_M 0x00000020
#define F_SPI_0034_MSTIR_V 0x1
#define F_SPI_0034_MSTIR_S 5

#define R_SPI_TXOICR		( __REG_SPI_BASE + 0x38 )

/**
 bitpos: [0]
 clear tx fifo overflow int
 */
#define F_SPI_0038_TXOICR 0x00000001
#define F_SPI_0038_TXOICR_M 0x00000001
#define F_SPI_0038_TXOICR_V 0x1
#define F_SPI_0038_TXOICR_S 0

#define R_SPI_RXOICR		( __REG_SPI_BASE + 0x3C )

/**
 bitpos: [0]
 clear rx fifo overflow int
 */
#define F_SPI_003C_RXOICR 0x00000001
#define F_SPI_003C_RXOICR_M 0x00000001
#define F_SPI_003C_RXOICR_V 0x1
#define F_SPI_003C_RXOICR_S 0

#define R_SPI_RXUICR		( __REG_SPI_BASE + 0x40 )

/**
 bitpos: [0]
 clear rx fifo underflow int
 */
#define F_SPI_0040_RXUICR 0x00000001
#define F_SPI_0040_RXUICR_M 0x00000001
#define F_SPI_0040_RXUICR_V 0x1
#define F_SPI_0040_RXUICR_S 0

#define R_SPI_MSTICR		( __REG_SPI_BASE + 0x44 )

/**
 bitpos: [0]
 clear spi master done int
 */
#define F_SPI_0044_MSTICR 0x00000001
#define F_SPI_0044_MSTICR_M 0x00000001
#define F_SPI_0044_MSTICR_V 0x1
#define F_SPI_0044_MSTICR_S 0

#define R_SPI_ICR		( __REG_SPI_BASE + 0x48 )

/**
 bitpos: [0]
 clear int
 */
#define F_SPI_0048_ICR 0x00000001
#define F_SPI_0048_ICR_M 0x00000001
#define F_SPI_0048_ICR_V 0x1
#define F_SPI_0048_ICR_S 0

#define R_SPI_DMACR		( __REG_SPI_BASE + 0x4C )

/**
 bitpos: [0]
 DMA start trigger
 */
#define F_SPI_004C_DMACR 0x00000001
#define F_SPI_004C_DMACR_M 0x00000001
#define F_SPI_004C_DMACR_V 0x1
#define F_SPI_004C_DMACR_S 0

#define R_SPI_DMACMDR		( __REG_SPI_BASE + 0x50 )

/**
 bitpos: [15:0]
 DMA spi command
 */
#define F_SPI_0050_SLV_CMD 0x0000FFFF
#define F_SPI_0050_SLV_CMD_M 0x0000FFFF
#define F_SPI_0050_SLV_CMD_V 0xFFFF
#define F_SPI_0050_SLV_CMD_S 0
/**
 bitpos: [16]
 DMA spi slave command length(per dfs)
 0: no slave command phase
 1: 1 dfs
 */
#define F_SPI_0050_SLV_CL 0x00010000
#define F_SPI_0050_SLV_CL_M 0x00010000
#define F_SPI_0050_SLV_CL_V 0x1
#define F_SPI_0050_SLV_CL_S 16

#define R_SPI_DMASAR		( __REG_SPI_BASE + 0x54 )

/**
 bitpos: [23:0]
 DMA spi slave address
 */
#define F_SPI_0054_SLV_A 0x00FFFFFF
#define F_SPI_0054_SLV_A_M 0x00FFFFFF
#define F_SPI_0054_SLV_A_V 0xFFFFFF
#define F_SPI_0054_SLV_A_S 0
/**
 bitpos: [25:24]
 DMA spi slave address length(per dfs)
 00: no slave address phase
 01: 1 dfs
 10: 2 dfs
 11: 3 dfs
 */
#define F_SPI_0054_SLV_AL 0x03000000
#define F_SPI_0054_SLV_AL_M 0x03000000
#define F_SPI_0054_SLV_AL_V 0x3
#define F_SPI_0054_SLV_AL_S 24
/**
 bitpos: [31:0]
 DMA IMB write address
 */

#define R_SPI_DMAMWAR		( __REG_SPI_BASE + 0x58 )

/**
 bitpos: [31:0]
 DMA IMB read address
 */

#define R_SPI_DMAMRAR		( __REG_SPI_BASE + 0x5C )


#define R_SPI_DMALATR		( __REG_SPI_BASE + 0x60 )

/**
 bitpos: [7:0]
 DMA IMB latency
 */
#define F_SPI_0060_DMALATR 0x000000FF
#define F_SPI_0060_DMALATR_M 0x000000FF
#define F_SPI_0060_DMALATR_V 0xFF
#define F_SPI_0060_DMALATR_S 0

#define R_SPI_SPI_LCD_IFL		( __REG_SPI_BASE + 0x64 )

/**
 bitpos: [0]
 1: Refer to ILI9341.pdf. Spi has 3 wire: cs, sclk, sda.
    Sda is a bi-didrectional io for txd, rxd.
 0: normal mode
 */
#define F_SPI_0064_SPI_LCD_IFL 0x00000001
#define F_SPI_0064_SPI_LCD_IFL_M 0x00000001
#define F_SPI_0064_SPI_LCD_IFL_V 0x1
#define F_SPI_0064_SPI_LCD_IFL_S 0
/**
 bitpos: [31:0]
 read  = rx fifo buffer
 write = tx fifo buffer
 */

#define R_SPI_DR_LOW		( __REG_SPI_BASE + 0x70 )


#define R_SPI_RX_SMP_DLY		( __REG_SPI_BASE + 0xF0 )

/**
 bitpos: [7:0]
 rxd sample delay
 */
#define F_SPI_00F0_RSD 0x000000FF
#define F_SPI_00F0_RSD_M 0x000000FF
#define F_SPI_00F0_RSD_V 0xFF
#define F_SPI_00F0_RSD_S 0

#define R_SPI_SPI_CTRLR0		( __REG_SPI_BASE + 0xF4 )

/**
 bitpos: [7:0]
 0x0: no dummy cycle
 0x1: 1 dummy cycle
 0x2: 2 dummy cycle
 …
 0xff: 127 dummy cycle
 */
#define F_SPI_00F4_DMY_CYC 0x000000FF
#define F_SPI_00F4_DMY_CYC_M 0x000000FF
#define F_SPI_00F4_DMY_CYC_V 0xFF
#define F_SPI_00F4_DMY_CYC_S 0

#define R_SPI_SPI_BI_SDA		( __REG_SPI_BASE + 0xF8 )

/**
 bitpos: [0]
 0x0: unididrectional sda
 0x1: bi-didrectional sda
 */
#define F_SPI_00F8_SPI_BI_SDA_0 0x00000001
#define F_SPI_00F8_SPI_BI_SDA_0_M 0x00000001
#define F_SPI_00F8_SPI_BI_SDA_0_V 0x1
#define F_SPI_00F8_SPI_BI_SDA_0_S 0
/**
 bitpos: [1]
 0x1: address&data phase dual io
 0x0: data phase dual io
 */
#define F_SPI_00F8_SPI_BI_SDA_1 0x00000002
#define F_SPI_00F8_SPI_BI_SDA_1_M 0x00000002
#define F_SPI_00F8_SPI_BI_SDA_1_V 0x1
#define F_SPI_00F8_SPI_BI_SDA_1_S 1

#define R_SPI_SPI_LSBF		( __REG_SPI_BASE + 0xFC )

/**
 bitpos: [0]
 0x0: MSB first
 0x1: LSB first
 */
#define F_SPI_00FC_SPI_LSBF 0x00000001
#define F_SPI_00FC_SPI_LSBF_M 0x00000001
#define F_SPI_00FC_SPI_LSBF_V 0x1
#define F_SPI_00FC_SPI_LSBF_S 0

#ifndef __KERNEL__
#ifdef __cplusplus
}
#endif
#endif

#endif  /* __SPI_REG_H__ */
